1. Field of the Invention
This invention relates to a spin injected diode and a spin injected field effect transistor which is made from two spin injected diodes.
2. Description of the Related Art
There are many kinds of devices that are used as nonvolatile storage cells, but all of them have weaknesses. Traditional technologies (older than ten years) include floating gate field effect transistors and ferroelectric capacitors. Floating gate technologies have slow write (10.sup.-5 to 10.sup.-4 sec) and erase (10.sup.-4 to 10.sup.-2 sec) times, and have limited write endurance (typically 10.sup.5 cycles). Ferroelectric approaches typically use destructive readout, have limited endurance and require a large voltage (5 V or more). Most ferroelectric cells require large areas and some designs suffer from limited retention. The read and write times are limited to the order of a few hundred nsec.
In the past few years, new approaches have been invented using magnetoelectronic technologies, i.e. electronic devices that incorporate one or more ferromagnetic (F) elements. One such category is all-metal magnetoresistive devices, sometimes called giant magnetoresistive (GMR) structures, which typically are trilayers with two F films and a nonmagnetic film N sandwiched in between. These are low impedance devices with two resistive states, R and R+.delta.R, separated by .delta.R/R.apprxeq.6 to 8%. To achieve voltage readout levels of order 1 to 10 mV, large currents must be driven through the patterned, multilayer wires. The readout times are relatively long, the readout power is relatively high, and electromigration that degrades the F-N interface is a limiting wearout mechanism. The layer thicknesses are typically a few nm, and must be controlled to the level of a few .ANG.. Since the two F films are exchange coupled through the N layer, reproducibility of device switching is problematic. Finally, device isolation, from others in an array, is poor and viable cell designs require an isolation transistor. Alternatively, a number of devices can be fabricated on a line with isolation transistors at each end of the line. However, the signal to noise ratio is diminished, read times are lengthened, and read power is increased.
Magnetic tunnel junctions (MTJ) form another popular device category. These are high impedance devices, with two F films separated by a thin dielectric barrier. The two resistive states, R and R+.delta.R, are separated by .delta.R/R.apprxeq.25 to 30% at low bias. The separation .delta.R/R decreases for larger bias, and is approximately 15% at bias voltages of 300 mV, giving readout voltages of about 40 mV. The chief advantage of MTJ devices over GMR structures is that MTJs can achieve conveniently large readout voltages. Typical impedances for devices of relevant dimensions are the order of 0.01 to 1 M.OMEGA.. The readout voltages have high Johnson noise, and readout can be slowed by long RC times. Device isolation is poor, and typical memory designs involve the use of a transistor. The resulting cell design requires a relatively large area. A greater problem is scalability. MTJs can be made with device impedance margins of about .+-.10% for a minimum feature size of f=1 to 2 .mu.m. To achieve reasonable impedance at smaller dimensions, a dielectric barrier with thickness of about 8 .ANG. is required. Device yield and uniformity with such thin dielectric layers is extremely poor. Because of this, and because of the problem of device isolation, it is unlikely that MTJs will be viable for high density nonvolatile memory arrays.
Another category of magnetoelectronic memory device involves hybrid structures of ferromagnetic metal and semiconductor components. One such device is the spin injected FET (SI FET), a field effect transistor (FET) with ferromagnetic source and drain described in U.S. Pat. No. 5,654,566 to Mark Johnson titled Magnetic Spin Injected Field Effect Transistor and Method of Operation. The source-drain conductance has two values for each of the two configurations corresponding to parallel and antiparallel orientation of the magnetizations of source and drain.
A second device is the "Hybrid Hall Effect Device" (HHE) as described in "Hybrid Hall Effect Device" by Mark Johnson, B. Bennett, M. J. Yang, M. M. Miller and B. V. Shanabrook, Appl. Phys. Lett. 71, (1997) and in U.S. Pat. No. 5,652,445 to Mark Johnson. This is a bilayer structure with an electrically isolated ferromagnetic film fabricated with one edge over the center of a Hall cross. The ferromagnetic element does not support any current transport. Rather, it acts as the source of a dipolar magnetic field that has a large perpendicular component B.sub.z, in the vicinity of the Hall cross. The local field B.sub.z, develops a Hall voltage V.sub.H in the semiconductor channel, and the sign of B.sub.z. and V.sub.H change when the in-plane magnetization of the ferromagnetic element is reversed. The write process uses current pulses applied through contiguous write wires, as described below, and the read process involves sensing V.sub.H, in the transverse arms of the Hall cross when a read bias pulse is applied to the longitudinal arms. The HHE has the advantage of relatively large readout voltages and a device impedance that can be tuned to a desirable value, e.g. in the range 1 to 100 k.OMEGA. and more preferable from 100 .OMEGA. to 10 k.OMEGA.. Furthermore, the cell involves a single thin film ferromagnetic element, which is insensitive to thickness changes on the order of 1 nm. The margins of reproducibility for switching fields, for device output, and for device impedance are narrow and yields are high. The HHE also shows inverse scalability with the device output increases as device dimensions shrink. A memory cell requires the addition of a (Schottky) diode to isolate the HHE device from other devices in an array.
3. Objects of the Invention
It is an object of this invention to provide a magnetoelectronic device appropriate for digital applications where the magnetic characteristic is not relatively difficult to engineer reproducibly.
It is a further object of this invention to provide a magnetoelectronic device appropriate for digital applications where the output of the device is proportional to the device impedance, and a required output level can be attained by tuning the device impedance.
It is a further object of this invention to provide a magnetoelectronic device appropriate for digital applications where the device can also be operated with the diode output voltage referenced to the interface resistance between the ferromagnetic layer and the semiconductor layer
It is a further object of this invention to provide a magnetoelectronic device appropriate for digital applications where the device can also be operated by flowing current through the channel and not through the interface and referencing the output voltage directly to the channel.
It is a further object of this invention to provide a magnetoelectronic device appropriate for digital applications where the device is fabricated with a single ferromagnetic film so that the magnetic properties of the single layer are more easily controlled.
It is a further object of this invention to provide a magnetoelectronic device appropriate for digital applications where the device has an intrinsic impedance that can be tuned within a range of convenient values.
It is a further object of this invention to provide a magnetoelectronic device appropriate for digital applications where the device has an impedance on the order of 1 K.OMEGA. to 100 K.OMEGA..
It is a further object of this invention to provide a magnetoelectronic device appropriate for digital applications where the single device made of suitable materials performs a storage function and an isolation function.
It is a further object of this invention to provide a magnetoelectronic device appropriate for digital applications wherein two diodes can be fabricated over a common, gated channel to form a spin injected FET.
These and further objects of the invention will become apparent as the description of the invention proceeds.